It is in general desirable to reduce the cost of a processing system, such as a chipset, particularly those for use in consumer devices, including for example mobile phones and other wireless devices. One way to achieve this is to share memory resources between several processor chips or chipsets by using a communication and memory sharing interface.
As a particular example, historically a modem module and an application engine module of a wireless device, such as a mobile phone or the like, have each been provided with their own dedicated external memory devices. However, as illustrated schematically in FIG. 1, it has been proposed to connect a modem module 100 of a wireless device, such as a mobile phone or the like, to an application engine (APE) module 110 of the wireless device via a communication and memory sharing interface (CMSI) 120, with the APE module 110 also being connected directly to a memory 130 of the wireless device via a memory interface 140. The modem module 100 has (indirect) access to the memory 130 via the CMSI 120 and the APE module 110. This means that dedicated memory resources (such as a dedicated synchronous dynamic random access memory (SDRAM) chip) need not be included specifically for the modem module 100 as such, or at least the amount of dedicated memory conventionally provided for the modem module 100 can be reduced, making the total components required for the modem module 100 in general both cheaper and physically smaller. CMSIs 120 may include, for example, chip-to-chip (C2C) interfaces or low latency interfaces (LLI), which both have low enough latencies to enable the modem module 100 to read from and write to the memory 130 rapidly via the interface 120. The modem module 100 may for example comprise one or more central processing units (CPU) 150 and optionally other modem hardware 160 which carry out baseband and radio frequency processing and handles signalling and also low level messaging to and from the network for the wireless device. The APE module 110 may for example comprise one or more APE CPUs 170 and optionally other APE hardware 180 which carry out application processing for the wireless device. One or both of the modem module 100 and the APE module 110 and/or one or more of the components thereof may be provided as a chipset, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc. It may be noted that the memory sharing interface and control/communication interface parts of the CMSI 120 may be provided as separate physical interfaces.
A modem module 100 sharing memory 130 with an APE module 110 will, however, typically place high bandwidth requirements and tight latency requirements on the CMSI 120, because some of the modem module 100 hardware components require inputs to and outputs from the memory 130 that are of very high bandwidth and/or that occur with high frequency. As a result of this, the CMSI 120 in this arrangement in general has a high power consumption. Furthermore, in order to support inputs and outputs that are of high frequency/bandwidth, CMSIs 120 generally need relatively large physical layer connections to the modem module 100 and the APE module 110, which requires a large number of input/output connection pins at both the modem module 100 and the APE module 110. This can increase the required size of these modules. In any event, where C2C or LLI or the like is used, there is a limit to the number of input and output pins available for the connection between the CMSI 120 and the modem module 100 and the APE module 110 according to C2C and LLI specifications.
Developing network technologies mean modem data rates are set to increase. Thus, if memory sharing is used between modem modules 100 and APE modules 110 as described above, then the bandwidth requirements placed on the CMSI 120 will be increased further, and, as a result, power consumption and the minimum chipset area will also increase.